Intel Transistor Technology with the World's First 45nm Processor

Intel Transistor Technology with the World's First 45nm Processor - 30 janvier 2007 - 13:19 (From Pierre Melquiot)

Intel Transistor Technology with the World's First 45nm Processor

Biggest Change to Computer Chips in 40 Years Means More Performance for Exponentially Less Cost. In one of the biggest advancements in fundamental transistor design, Intel will use dramatically different transistor materials to build the hundreds of millions of microscopic 45 nanometer (nm) transistors inside the next generation of the company's Intel Core2 family of processors. Intel already has the world's first 45nm CPUs in-house - the first of at least fifteen 45nm processor products in development. This new transistor breakthrough will allow Intel to continue delivering record-breaking PC, laptop and server processor speeds while reducing the amount of electrical leakage from transistors that can hamper chip and PC design, size, power consumption, noise and costs. It also ensures that Moore's Law, a high-tech industry axiom that transistor counts double about every two years to deliver ever more functionality at exponentially decreasing cost, thrives well into the next decade.

By using a new material combination of high-k gate dielectrics and metal gates, Intel's 45nm transistors significantly improve performance to deliver faster multi-core processors that consume less power. Intel's demonstration of a functional 45nm CPU underscores its process technology lead of more than a year over the rest of the semiconductor industry. The world's first working 45nm processors (next generation Intel Core2 family processors - codenamed "Penryn") are already running multiple operating systems (Windows Vista, Mac OS X, Windows XP and Linux) and various applications. Intel is on track for 45nm production in the second half of 2007.

According to Intel co-founder Gordon Moore, "The implementation of high-k and metal materials marks the biggest change in transistor technology since the introduction of polysilicon gate MOS transistors in the late 1960s."

Compared to today's 65nm technology, Intel's 45nm technology will provide the following product benefits: Approximately twice the transistor density (great for smaller chip sizes or increased transistor counts) ; Approximately 30 percent reduction in transistor-switching power ; Greater than 20 percent improvement in transistor-switching speed or a greater than 5 times reduction in source-drain leakage power ; Greater than 10 times reduction in transistor gate oxide leakage for lower power requirements and increased battery life.

To understand the full significance of Intel's achievement, it helps to know that transistors are the tiny switches that process the ones and zeroes of the digital world. A gate is used to turn transistors on and off, and the gate dielectric is an insulator underneath the gate. The gate dielectric's job is to separate (insulate) the gate from the channel where the current flows.

Intel's innovative combination of the metal gates and the high-k gate dielectrics represents a major milestone as the industry races to reduce electrical current leakage in transistors - a growing problem for chip manufacturers as transistors get ever smaller. Many in the industry have been working for the past several years to find the correct combination (out of hundreds of candidates) of new materials, but Intel is the first to successfully implement such a combination in its 45nm process.

The industry has been using silicon dioxide (SiO2) to build transistor gate dielectrics. Intel's SiO2 gate dielectrics, which have been the thinnest in the industry for the past 14 years, are now only 1.2nm thick (equal to 5 atomic layers) in our 65nm process. However, as the gate dielectric gets thinner, leakage increases. Transistor gate leakage associated with the ever-thinning gate dielectric made of SiO2 has been recognized by the industry as one of the most formidable technical challenges facing Moore's Law in this decade. Intel's solution is to move to alternate materials that are thicker to address leakage, yet at the same time preserve the high capacitance that is desirable for good transistor performance. This class of materials have a property known by the moniker "high-k." High-k, though, is not to be confused with low-k, which is being used to insulate on-chip interconnects. In transistor gate dielectrics, high-k is desirable as it gives high performance with low leakage; in interconnects, low-k is desirable as it leads to faster signal transmission times.

For its 45nm technology, Intel is using a hafnium-based high-k material in the gate dielectric. The high-k dielectric is created using atomic layer deposition (ALD) whereby a single layer of the high-k material molecule is deposited at a time. Because the high-k gate dielectric isn't compatible with today's silicon gate electrode, Intel had to develop the new metal gate materials to solve two fundamental problems that arise when the two are combined. One is known as "threshold voltage pinning" (also called "Fermi level pinning") and the other is "phonon scattering." Neither of these effects is desirable and both cause lower transistor performance. These effects arise when a high-k dielectric is used with a polysilicon gate electrode, but are significantly improved when polysilicon is replaced by specific metals (different ones for NMOS and PMOS transistors), and all are integrated with the right process recipe. (The specific metals are a trade secret.)

The combination of the metal gates and the high-k gate dielectric leads to transistors with very low current leakage and high performance.

Intel will use copper wires with a low-k dielectric for its 45nm interconnects for increased performance and lower power consumption. We will also use innovative design rules and advanced mask techniques to extend the use of 193nm dry lithography because of its cost advantages and high-volume manufacturing capabilities.

Intel's is currently developing its 45nm process on 300mm wafers in Hillsboro, Oregon, in D1D, a fab with clean-room space equivalent to 3.5 football fields. Two new 300mm fabs are being built for the coming 45nm ramp: Fab 32 in Ocotillo, Arizona (production due to start in the second half of 2007) and Fab 28 in Israel (production to start in the first half of 2008).

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